Product Id: 18170498
Description: Cisco 1-Port Channelized OC-3/STM-1 Circuit Emulation Over Packet and Channelized ATM Shared Port Adapter - Expansion module - ATM, SONET/SDH - OC-3c/STM-1 - for Cisco 7603, 7603-S, 7604, 7606, 7606-S, 7609, 7609-S, 7613
Mfr Part #: SPA-1CHOC3-CE-ATM=
The Cisco I-Flex design combines shared port adapters (SPAs) and SPA interface processors (SIPs), using an extensible design that enables service prioritization for voice, video, and data services. Enterprise and service provider customers can use the improved slot economics resulting from modular port adapters that are interchangeable across Cisco routing platforms. The I-Flex design maximizes connectivity options and offers superior service intelligence through programmable interface processors, which deliver line-rate performance. I-Flex enhances speed-to-service revenue and provides a rich set of quality-of-service (QoS) features for premium service delivery while effectively reducing the overall cost of ownership.
The Cisco 1-port Channelized OC3/STM-1 circuit emulation over packet and ATM SPA is available on high-end Cisco routing platforms offering the benefits of network scalability with lower initial costs and ease of upgrades. The Cisco SPA/SIP portfolio continues the Cisco focus on investment protection along with consistent feature support, broad interface availability, and the latest technology. The Cisco SPA/SIP portfolio allows different interfaces to be deployed on the same interface processor.
The Circuit Emulation over Packet (CEoP) SPAs provide a new service offering. These SPAs provide bit-transparent data transport that is completely protocol independent.
For the first time, this allows network administrators to use their existing IP/MPLS network to provide leased-line emulation services or to carry data streams or protocols that do not meet the format requirements of other multiservice platform interfaces. In addition, these SPAs can be used for low-speed ATM services, including Inverse Multiplexing over ATM (IMA).
- Jitter and wander compliant to ITU G.823/824 traffic interface
- Compliant to IETF RFC 4553: Structure-Agnostic TDM over Packet (SAToP)
- Bit-transparent data transport
- Protocol-independent data transport
- Supports CEoP PWE (CESoPSN and SAToP) transport using Real-Time Transport Protocol (RTP)
- QoS using MPLS EXP
- Configurable payload size
- Synchronous, differential, and adaptive clock recovery schemes, with clock accuracy target of 15ppb
- Configurable jitter buffer up to 320 milliseconds
- Configurable idle pattern
- Support for ATM traffic classes: UBR, UBR+, VBR-nrt, VBR-rt, CBR
- Support for ATM QoS - VC and VP shaping
- Support for ATM IMA
- Support for ATM PWE (VC and VP mode cell relay)
- Support for ATM UNI (3.0, 3.1)
- Overall SPA status LEDs
- Per-port status LEDs
- Protocol-independent data transport
These SPAs provide completely bit-transparent, bidirectional, point-to-point data transport. Every bit presented to an ingress port is transported unchanged to the corresponding egress port by encapsulating the data bits into a PWE packet for transport across an IP/MPLS network. The data ports do not care about the structure or content of the data stream. Consequently, these SPAs are ideally suited to transport data streams that are not suited to be carried using other platform interfaces.
- Data integrity
Because these SPAs do not consider the content of any circuit emulation data stream, it is important to engineer the transport network in such a way as to minimize the risk of losing any data packets. To help ensure that a data stream is delivered, without gaps, to the destination CPE, data packets are held in a dejitter buffer at the destination port to eliminate any delay variation (that is, jitter) experienced by successive packets traveling through the network.
- Flexibility in delay vs. overhead
These SPAs support a wide variety of payload sizes from 32 bytes (for very low-speed data streams) to 1312 bytes. This provides the user the ability to control the overall efficiency as well as the end-to-end delay of the system by controlling the packetization delay.
- Clocking flexibility
For circuit emulation services, In order to achieve bit-transparent circuit emulation without bit errors, it is imperative that both endpoints of the circuit use the same bit clock frequency. The network should be synchronized end to end for proper operation.